For a MOS capacitor, $V_{fb}$ and $V_t$ are the flat-band voltage and the threshold voltage, respectively. The variation of the depletion width ($W_{\text{dep}}$) for varying gate voltage ($V_g$) is best represented by
Extrinsic semiconductors are made by doping pure or intrinsic semiconductors with suitable impurity. There are two types of dopants used in doping, Si or Ge, and using them p-type and n-type semiconductors can be obtained. A p-n junction is the basic building block of many semiconductor devices. Two important processes occur during the formation of a p-n junction: diffusion and drift. When such a junction is formed, a ’depletion layer’ is created consisting of immobile ion-cores. This is responsible for a junction potential barrier. The width of a depletion layer and the height of potential barrier changes when a junction is forward-biased or reverse-biased. A semiconductor diode is basically a p-n junction with metallic contacts provided at the ends for application of an external voltage. Using diodes, alternating voltages can be rectified.
Here are two analogous groups, Group-I and Group-II, that list words in their decreasing order of intensity. Identify the missing word in Group-II.
Abuse \( \rightarrow \) Insult \( \rightarrow \) Ridicule
__________ \( \rightarrow \) Praise \( \rightarrow \) Appreciate
Two resistors are connected in a circuit loop of area 5 m\(^2\), as shown in the figure below. The circuit loop is placed on the \( x-y \) plane. When a time-varying magnetic flux, with flux-density \( B(t) = 0.5t \) (in Tesla), is applied along the positive \( z \)-axis, the magnitude of current \( I \) (in Amperes, rounded off to two decimal places) in the loop is (answer in Amperes).
A 50 \(\Omega\) lossless transmission line is terminated with a load \( Z_L = (50 - j75) \, \Omega.\) { If the average incident power on the line is 10 mW, then the average power delivered to the load
(in mW, rounded off to one decimal place) is} _________.
In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns. The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is (answer in MHz).