Step 1: The intrinsic resistivity \( \rho_i \) of a semiconductor is given by the formula: \[ \rho_i = \frac{1}{q \cdot n_i \cdot (\mu_e + \mu_h)} \] where:
\( q \) is the charge of an electron \( (1.6 \times 10^{-19} \, C) \),
\( n_i \) is the intrinsic carrier concentration \( (2.5 \times 10^{16} / m^3) \),
\( \mu_e \) is the electron mobility \( (0.15 \, {m}^2/{Vs}) \),
\( \mu_h \) is the hole mobility \( (0.05 \, {m}^2/{Vs}) \).
Step 2: Substituting the values into the formula: \[ \rho_i = \frac{1}{(1.6 \times 10^{-19}) \cdot (2.5 \times 10^{16}) \cdot (0.15 + 0.05)} = \frac{1}{(1.6 \times 10^{-19}) \cdot (2.5 \times 10^{16}) \cdot (0.2)} \] \[ \rho_i = \frac{1}{8 \times 10^{-3}} = 0.125 \, \Omega \cdot m \] To convert to \( k\Omega \cdot m \), we multiply by 1000: \[ \rho_i = 1.25 \, k\Omega \cdot m \] Thus, the correct answer is 1.25.
Extrinsic semiconductors are made by doping pure or intrinsic semiconductors with suitable impurity. There are two types of dopants used in doping, Si or Ge, and using them p-type and n-type semiconductors can be obtained. A p-n junction is the basic building block of many semiconductor devices. Two important processes occur during the formation of a p-n junction: diffusion and drift. When such a junction is formed, a ’depletion layer’ is created consisting of immobile ion-cores. This is responsible for a junction potential barrier. The width of a depletion layer and the height of potential barrier changes when a junction is forward-biased or reverse-biased. A semiconductor diode is basically a p-n junction with metallic contacts provided at the ends for application of an external voltage. Using diodes, alternating voltages can be rectified.
Here are two analogous groups, Group-I and Group-II, that list words in their decreasing order of intensity. Identify the missing word in Group-II.
Abuse \( \rightarrow \) Insult \( \rightarrow \) Ridicule
__________ \( \rightarrow \) Praise \( \rightarrow \) Appreciate
A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input \( P_0 \) is set to logic ‘0’ and \( P_1 \) is set to logic ‘1’ at all times. The timing diagram of the inputs \( SEL \) and \( S \) are also shown below. The sequence of output \( Y \) from time \( T_0 \) to \( T_3 \) is _________.

Consider a part of an electrical network as shown below. Some node voltages, and the current flowing through the \( 3\,\Omega \) resistor are as indicated.
The voltage (in Volts) at node \( X \) is _________.
