A full adder is a digital circuit that adds two binary digits and a carry-in. However, in this circuit, \( Z \) is connected to the carry-in input and is set to logic ‘1’. This configuration will cause the circuit to subtract \( Y \) from \( X \).
Here's why:
The XOR gate is used to perform a subtraction operation in digital circuits, where the input \( X \) and \( Y \) are processed with the logic ‘1’ carry-in (i.e., the full adder behaves like a subtractor with the carry-in being ‘1’).
In this case, \( X \) and \( Y \) will be subtracted, producing the desired difference.
Thus, the overall circuit functions as a subtractor when \( Z \) is set to ‘1’. Hence, the correct answer is (B).
In the digital circuit shown in the figure, for the given inputs the P and Q values are:
The truth table corresponding to the circuit given below is
The Boolean expression $\mathrm{Y}=\mathrm{A} \overline{\mathrm{B}} \mathrm{C}+\overline{\mathrm{AC}}$ can be realised with which of the following gate configurations.
A. One 3-input AND gate, 3 NOT gates and one 2-input OR gate, One 2-input AND gate
B. One 3-input AND gate, 1 NOT gate, One 2-input NOR gate and one 2-input OR gate
C. 3-input OR gate, 3 NOT gates and one 2-input AND gate
Choose the correct answer from the options given below:
The value of current \( I \) in the electrical circuit as given below, when the potential at \( A \) is equal to the potential at \( B \), will be _____ A.
Here are two analogous groups, Group-I and Group-II, that list words in their decreasing order of intensity. Identify the missing word in Group-II.
Abuse \( \rightarrow \) Insult \( \rightarrow \) Ridicule
__________ \( \rightarrow \) Praise \( \rightarrow \) Appreciate
Two resistors are connected in a circuit loop of area 5 m\(^2\), as shown in the figure below. The circuit loop is placed on the \( x-y \) plane. When a time-varying magnetic flux, with flux-density \( B(t) = 0.5t \) (in Tesla), is applied along the positive \( z \)-axis, the magnitude of current \( I \) (in Amperes, rounded off to two decimal places) in the loop is (answer in Amperes).
A 50 \(\Omega\) lossless transmission line is terminated with a load \( Z_L = (50 - j75) \, \Omega.\) { If the average incident power on the line is 10 mW, then the average power delivered to the load
(in mW, rounded off to one decimal place) is} _________.
In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns. The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is (answer in MHz).