From the CMOS circuit:
- Pull-down (NMOS) side has M2 and M3 in series (representing AND: BC) and in parallel with M1 (OR with A), giving \( A + BC \).
- Pull-up (PMOS) side is the complement logic.
The output Y is the complement of the NMOS pull-down logic:
\[
Y = \overline{A + BC}
\]
This is a standard CMOS implementation of a NOR-type combination.