Question

The ideal long-channel nMOSFET and pMOSFET devices shown have threshold voltages of $1\text{ V}$ and $-1\text{ V}$, respectively. The MOSFET substrates are connected to their sources. Ignore leakage currents and assume that the capacitors are initially discharged. For the applied voltages as shown, the steady-state voltages are ________________.

• A. $V_1=5\text{ V},\quad V_2=5\text{ V}$
• B. $V_1=5\text{ V},\quad V_2=4\text{ V}$
• C. $V_1=4\text{ V},\quad V_2=5\text{ V}$
• D. $V_1=4\text{ V},\quad V_2=-5\text{ V}$

Hint:

For MOSFET–capacitor charging circuits, the voltage stops rising when the MOSFET reaches cutoff. For nMOS cutoff occurs when $V_{GS}=V_T$, and for pMOS when $V_{SG}=|V_T|$.

Answer 1

The Correct Option is C

Step 1: Analyze the nMOSFET circuit (left side).
The gate and drain of the nMOSFET are both connected to $5\text{ V}$. The source is connected to node $V_1$, which is initially $0$ (capacitor discharged). For an nMOSFET: \[ \text{Turn ON if } V_{GS} \ge V_{TN} = 1\text{ V}. \] Initially: \[ V_{GS} = 5 - 0 = 5\text{ V}>1\text{ V} \Rightarrow \text{MOSFET is ON}. \] As the capacitor charges, $V_1$ increases. The transistor will remain ON until \[ V_{GS} = 5 - V_1<1. \] At cutoff condition: \[ 5 - V_1 = 1 \quad \Rightarrow \quad V_1 = 4\text{ V}. \] Once $V_1$ reaches $4\text{ V}$, the gate-to-source voltage becomes exactly the threshold value and the MOSFET turns OFF. Thus, the capacitor cannot charge beyond $4\text{ V}$. Therefore, \[ V_1 = 4\text{ V}. \] Step 2: Analyze the pMOSFET circuit (right side).
The gate and drain of the pMOSFET are both connected to $-5\text{ V}$ and $5\text{ V}$ respectively. Source is at $5\text{ V}$ and node $V_2$ starts at $0$. For a pMOSFET: \[ \text{Turn ON if } V_{SG} \ge |V_{TP}| = 1\text{ V}. \] Here \[ V_{SG} = 5 - (-5) = 10\text{ V} \Rightarrow \text{strongly ON}. \] As the capacitor charges upward from $0$ toward $5\text{ V}$, the source is fixed at $5\text{ V}$. But the pMOSFET can only pull node $V_2$ upward toward the source voltage. The device turns OFF only when \[ V_{SG}<1. \] Since the gate is at $-5\text{ V}$ and source is at $5\text{ V}$, we have \[ V_{SG} = 5 - (-5) = 10\text{ V}, \] which never decreases because source and gate voltages are fixed. Thus, pMOSFET remains ON and charges $V_2$ fully to the source voltage: \[ V_2 = 5\text{ V}. \] Step 3: Final steady-state values.
\[ V_1 = 4\text{ V}, \qquad V_2 = 5\text{ V}. \] This corresponds to option (C).
Final Answer: $V_1=4\text{ V},\ V_2=5\text{ V}$