In the circuit shown below, switch S was closed for a long time. If the switch is opened at $t=0$, the maximum magnitude of the voltage $V_R$, in volts, is _____________ (rounded off to the nearest integer).
Explain the principle of Wheatstone's bridge by Kirchhoff's law. In the given circuit, there is no deflection in the galvanometer \( G \). What is the current flowing through the cell?
Three ac circuits are shown in the figures with equal currents. Explain with reason, if the frequency of the voltage \( E \) is increased then what will be the effect on the currents in them.
What is the first law of Kirchhoff of the electrical circuit? Find out the potential difference between the ends of 2 \(\Omega\) resistor with the help of Kirchhoff's law. See the figure:
State Kirchhoff's law related to electrical circuits. In the given metre bridge, balance point is obtained at D. On connecting a resistance of 12 ohm parallel to S, balance point shifts to D'. Find the values of resistances R and S.
With the help of the given circuit, find out the total resistance of the circuit and the current flowing through the cell.
Here are two analogous groups, Group-I and Group-II, that list words in their decreasing order of intensity. Identify the missing word in Group-II.
Abuse \( \rightarrow \) Insult \( \rightarrow \) Ridicule
__________ \( \rightarrow \) Praise \( \rightarrow \) Appreciate
Two resistors are connected in a circuit loop of area 5 m\(^2\), as shown in the figure below. The circuit loop is placed on the \( x-y \) plane. When a time-varying magnetic flux, with flux-density \( B(t) = 0.5t \) (in Tesla), is applied along the positive \( z \)-axis, the magnitude of current \( I \) (in Amperes, rounded off to two decimal places) in the loop is (answer in Amperes).
A 50 \(\Omega\) lossless transmission line is terminated with a load \( Z_L = (50 - j75) \, \Omega.\) { If the average incident power on the line is 10 mW, then the average power delivered to the load
(in mW, rounded off to one decimal place) is} _________.
In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns. The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is (answer in MHz).