List of top Computer Organization and Architecture Questions

Consider the following operations on an initially empty stack:
Push 10
Push 20
Pop
Push 30
Pop
Push 40

What is the final content of the stack?

Which of the following is true about the binary search algorithm when applied to a sorted array?

Given a pipeline with 5 stages, the delay for each stage is as follows:

\[ \begin{array}{|c|c|} \hline \textbf{Stage} & \textbf{Delay (ns)} \\ \hline 1 & 250 \\ 2 & 150 \\ 3 & 100 \\ 4 & 200 \\ 5 & 50 \\ \hline \end{array} \]

The buffer delay is 10 ns. Find the time for \( n = 1000 \) instructions.

In an IPv4 packet, if \( X \) is written in the protocol field, which of the following is not a valid protocol \( X \)?

What is included in the Instruction Set Architecture (ISA)?

Let \(Z_n\) be the group of integers \(\{0, 1, 2, \dots, n - 1\}\) with addition modulo \(n\) as the group operation. The number of elements in the group \(Z_2 \times Z_3 \times Z_4\) that are their own inverses is ............

A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program \(P\). The unit is then redesigned to operate on a 5-stage pipeline at 2 GHz. Assume that the ideal throughput of the pipelined unit is 1 instruction per cycle. In the execution of program \(P\), 20\% instructions incur an average of 2 cycles stall due to data hazards and 20\% instructions incur an average of 3 cycles stall due to control hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is ............

A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below. R-type Instruction Format: \begin{center} \setlength{\tabcolsep}{15pt} % Adjust column spacing \renewcommand{\arraystretch}{1.5} % Adjust row spacing \begin{tabular}{|c|c|c|c|c|} \hline OPCODE & UNUSED & DST Register & SRC Register1 & SRC Register2
\hline \end{tabular} \end{center} \vspace{0.5cm} I-type Instruction Format: \begin{center} \setlength{\tabcolsep}{15pt} % Adjust column spacing \renewcommand{\arraystretch}{1.5} % Adjust row spacing \begin{tabular}{|c|c|c|c|} \hline OPCODE & DST Register & SRC Register & \# Immediate Value/Address
\hline \end{tabular} \end{center} In the OPCODE, 1 bit is used to distinguish between I-type and R-type instructions, and the remaining bits indicate the operation. The processor has 50 architectural registers, and all register fields in the instructions are of equal size. Let \(X\) be the number of bits used to encode the UNUSED field, \(Y\) be the number of bits used to encode the OPCODE field, and \(Z\) be the number of bits used to encode the immediate value/address field. The value of \(X + 2Y + Z\) is ............

A processor with 16 general-purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a 16-bit scalar field. If 8 addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is ............

An instruction format has the following structure: \begin{center} Instruction Number: Opcode destination reg, source reg-1, source reg-2} \end{center} Consider the following sequence of instructions to be executed in a pipelined processor: I\(_1\): DIV R3, R1, R2
I\(_2\): SUB R5, R3, R4
I\(_3\): ADD R3, R5, R6
I\(_4\): MUL R7, R3, R8 Which of the following statements is/are TRUE?

Which of the following statements is/are FALSE?}

Node X has a TCP connection open to node Y. The packets from X to Y go through an intermediate IP router R. Ethernet switch S is the first switch on the network path between X and R. Consider a packet sent from X to Y over this connection. Which of the following statements is/are TRUE about the destination IP and MAC addresses on this packet at the time it leaves X?

Let \( T(n) \) be the recurrence relation defined as follows: \[ T(0) = 1, \quad T(1) = 2, \quad T(n) = 5T(n-1) - 6T(n-2) \quad \text{for } n \geq 2 \] Which one of the following statements is TRUE?

The format of a single-precision floating-point number as per the IEEE 754 standard is:} \begin{center} \begin{tabular}{|c|c|c|} \hline Sign (1 bit) & Exponent (8 bits) & Mantissa (23 bits)
\hline \end{tabular} \end{center} Choose the largest floating-point number among the following options:

Consider a computer with a \(4 \, \text{MHz}\) processor. Its DMA controller can transfer \(8 \, \text{bytes}\) in \(1\) cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second}) of the DMA controller if \(1\%\) of the processor cycles are used for DMA?

The values of x and y, if (x 567)₈+ (2yx5)₈ = (71yx)₈

When even parity ASCII text is transmitted asynchronously at a rate of 10 characters per sec. over a 110-bps line, what percentage of the received bits actually contain data

MS Access is a

Match List-I and List-II

LIST I		LIST II
A.	Dynamic RAM	I.	Know as non-volatile memory and can be programmed
B.	PROM	II.	non-volatile and Random access digital Data storage device
C.	HDD	III.	is made up of memory cells where each cell is composed of one capacitor and one transistor
D.	Static Ram	IV.	It remains the data as long as power is provided to the memory chip.

Choose the correct answer from the options given below:

In a memory mapped I/O system, which of the following will not be there?

Match List-I and List-II

LIST I		LIST II
A.	Binary coded Decimal	I.	4 bits are used to represent each digit
B.	ASCII	II.	Characters are represented by eight bits
C.	EBCDIC	III.	Character set supports Japanese and Chinese fonts
D.	UNICODE	IV.	Standard character codes used to store data

Choose the correct answer from the options given below:

Match List-I and List-II

LIST I		LIST II
A.	(123)s	I.	(0001 1111 1100)₂
B.	(IFC)₁₆	II.	(0011001)₂
C.	(25)₁₀	III.	(0001 0010 0011)₂
D.	(123)₁₆	IV.	(001 010 011)₂

Choose the correct answer from the options given below:

Which of the following binary numbers are divisible by 4?
(A) 10101010101010
(B) 1110001110001
(C) 11001010100
(D) 1111000011
(E) 10010 1100

Given below are two statements:
Statement I: Cache memory is a very high speed memory placed in between CPU and Hard Disk.
Statement II: One major advantage of virtual memory is that programs can be larger than main memory.
In the light of the above Statements, choose the most appropriate answer from the options given below :

Given below are two statements:
Statement I: 011010 is 2's complement representation of -37.
Statement II: (211)_s is octal representation of 137.
In the light of the above Statements, choose the most appropriate answer from the options given below :