Question

An instruction format has the following structure: \begin{center} Instruction Number: Opcode destination reg, source reg-1, source reg-2} \end{center} Consider the following sequence of instructions to be executed in a pipelined processor: I\(_1\): DIV R3, R1, R2
I\(_2\): SUB R5, R3, R4
I\(_3\): ADD R3, R5, R6
I\(_4\): MUL R7, R3, R8 Which of the following statements is/are TRUE?

• A. There is a RAW dependency on R3 between I\(_1\) and I\(_2\)
• B. There is a WAR dependency on R3 between I\(_1\) and I\(_3\)
• C. There is a RAW dependency on R3 between I\(_2\) and I\(_3\)
• D. There is a WAW dependency on R3 between I\(_3\) and I\(_4\)

Hint:

To identify dependencies, carefully analyze the source and destination registers used by consecutive instructions.

Answer 1

The Correct Option is A

Option (A): True. Instruction I\(_1\) writes to R3, and instruction I\(_2\) reads from R3, creating a Read After Write (RAW) dependency between I\(_1\) and I\(_2\).
Option (B): False. Instruction I\(_3\) writes to R3, but I\(_1\) also writes to R3. This would be a Write After Write (WAW) dependency, not a WAR dependency.
Option (C): False. Instruction I\(_3\) writes to R3, but I\(_2\) does not read R3. Hence, there is no RAW dependency between I\(_2\) and I\(_3\).
Option (D): False. Both I\(_3\) and I\(_4\) write to R3, creating a Write After Write (WAW) dependency, but this dependency does not exist in the given instruction sequence. Final Answer: \[ \boxed{\text{(A)}} \]