List of top Computer Organization and Architecture Questions

Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements:
\[ S_1:\ \text{Read misses in a write-through L1 cache do not result in writebacks of dirty lines to the L2.} \] \[ S_2:\ \text{Write allocate policy must be used in conjunction with write-through caches and no-write allocate policy is used with writeback caches.} \] Which of the following statements is correct?
Consider a computer system with DMA support.
The DMA module transfers one 8-bit character in one CPU cycle using cycle stealing. The processor speed is 2 MHz and 0.5% of processor cycles are used for DMA. The data transfer rate of the device is \(\underline{\hspace{2cm}}\) bits per second.
Consider a set-associative cache of size 2KB with cache block size of 64 bytes. If the width of the tag field is 22 bits, the associativity of the cache is \(\underline{\hspace{2cm}}\).
Instruction format has the following structure.Instruction number OPCODE destination Source \(1\) and Source \(2\).
\(I_1:\) Div \(R_3 R_1 R_2;\)
\(I_2:\) Sub \(R_5 R_3 R_4;\)
\(I_3:\) Add \(R_3 R_5 R_6;\)
\(I_4:\) Mul \(R_7 R_3 R_8;\)