The $\dfrac{V_{OUT}}{V_{IN}}$ of the circuit shown below is _____________
Step 1: Identify the rightmost stage.
The rightmost op-amp has its non-inverting input at ground, input resistor $R_3$ to the inverting input, and feedback $R_4$ from output to inverting input $\Rightarrow$ inverting amplifier: \[ V_{OUT}=-\frac{R_4}{R_3}\,v_x, \] where $v_x$ is the signal applied through $R_3$.
Step 2: Evaluate $v_x$ from the left block.
Each of the two left op-amps has its inverting input fed back from its own output (via $R_2$) $\Rightarrow$ both act as voltage followers. Top follower outputs $v_a=V_{IN}$; bottom follower (non-inverting at $0$ V) outputs $v_b=0$. The resistor $R_3$ feeding the right stage is connected between these two follower outputs, so the voltage impressed across the input resistor is \[ v_x=v_a-v_b=V_{IN}-0=V_{IN}. \] Step 3: Overall gain.
Substitute $v_x=V_{IN}$ in Step 1: \[ \frac{V_{OUT}}{V_{IN}}=-\frac{R_4}{R_3}. \] \[ \boxed{-\dfrac{R_4}{R_3}} \]
In the circuit below, the voltage $V_L$ is ______________ V (rounded off to two decimal places).} 
A sample and hold circuit is implemented using a resistive switch and a capacitor with a time constant of 1 $\mu$s. The time for the sampling switch to stay closed to charge a capacitor adequately to a full scale voltage of 1 V with 12-bit accuracy is ____________ $\mu$s (rounded off to two decimal places).
The h-parameters of a two port network are shown below. The condition for the maximum small signal voltage gain $\dfrac{V_{out}}{V_s}$ is _____________
In the circuit shown below, $V_1$ and $V_2$ are bias voltages. Based on input and output impedances, the circuit behaves as a 
Here are two analogous groups, Group-I and Group-II, that list words in their decreasing order of intensity. Identify the missing word in Group-II.
Abuse \( \rightarrow \) Insult \( \rightarrow \) Ridicule
__________ \( \rightarrow \) Praise \( \rightarrow \) Appreciate
A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input \( P_0 \) is set to logic ‘0’ and \( P_1 \) is set to logic ‘1’ at all times. The timing diagram of the inputs \( SEL \) and \( S \) are also shown below. The sequence of output \( Y \) from time \( T_0 \) to \( T_3 \) is _________.

Consider a part of an electrical network as shown below. Some node voltages, and the current flowing through the \( 3\,\Omega \) resistor are as indicated.
The voltage (in Volts) at node \( X \) is _________.
