In the circuit shown below, $V_1$ and $V_2$ are bias voltages. Based on input and output impedances, the circuit behaves as a
In the circuit below, the voltage $V_L$ is ______________ V (rounded off to two decimal places).}
A sample and hold circuit is implemented using a resistive switch and a capacitor with a time constant of 1 $\mu$s. The time for the sampling switch to stay closed to charge a capacitor adequately to a full scale voltage of 1 V with 12-bit accuracy is ____________ $\mu$s (rounded off to two decimal places).
The h-parameters of a two port network are shown below. The condition for the maximum small signal voltage gain $\dfrac{V_{out}}{V_s}$ is _____________
The $\dfrac{V_{OUT}}{V_{IN}}$ of the circuit shown below is _____________
Here are two analogous groups, Group-I and Group-II, that list words in their decreasing order of intensity. Identify the missing word in Group-II.
Abuse \( \rightarrow \) Insult \( \rightarrow \) Ridicule
__________ \( \rightarrow \) Praise \( \rightarrow \) Appreciate
Two resistors are connected in a circuit loop of area 5 m\(^2\), as shown in the figure below. The circuit loop is placed on the \( x-y \) plane. When a time-varying magnetic flux, with flux-density \( B(t) = 0.5t \) (in Tesla), is applied along the positive \( z \)-axis, the magnitude of current \( I \) (in Amperes, rounded off to two decimal places) in the loop is (answer in Amperes).
A 50 \(\Omega\) lossless transmission line is terminated with a load \( Z_L = (50 - j75) \, \Omega.\) { If the average incident power on the line is 10 mW, then the average power delivered to the load
(in mW, rounded off to one decimal place) is} _________.
In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns. The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is (answer in MHz).