List of top Computer Organization and Architecture Questions asked in GATE CS

A cache memory that has a hit rate of 0.8 has an access latency of 10 ns and a miss penalty of 100 ns. An optimization is done on the cache to reduce the miss rate. However, the optimization results in an increase of cache access latency to 15 ns, whereas the miss penalty is not affected. The minimum hit rate (rounded off to two decimal places) needed after the optimization such that it should not increase the average memory access time is \(\underline{\hspace{1cm}}\).
Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a write through cache. Which of the following statements is/are FALSE?

Consider the following instruction sequence where registers \( R1 \), \( R2 \), and \( R3 \) are general purpose and MEMORY[X] denotes the content at the memory location \( X \): 
\[\begin{array}{|l|l|c|} \hline \textbf{Instruction} & \textbf{Semantics} & \textbf{Instruction Size (bytes)} \\ \hline \text{MOV R1, (5000)} & \text{\( R1 \leftarrow \text{MEMORY}[5000] \)} & \text{4} \\ \hline \text{MOV R2, (R3)} & \text{\( R2 \leftarrow \text{MEMORY}[R3] \)} & \text{4} \\ \hline \text{ADD R2, R1} & \text{\( R2 \leftarrow R1 + R2 \)} & \text{2} \\ \hline \text{MOV (R3), R2} & \text{\( \text{MEMORY}[R3] \leftarrow R2 \)} & \text{4} \\ \hline \text{INC R3} & \text{\( R3 \leftarrow R3 + 1 \)} & \text{2} \\ \hline \text{DEC R1} & \text{\( R1 \leftarrow R1 - 1 \)} & \text{2} \\ \hline \text{BNZ 1004} & \text{Branch if not zero to the given absolute address} & \text{2} \\ \hline \text{HALT} & \text{Stop} & \text{1} \\ \hline \end{array}\]Assume that the content of memory location 5000 is 10, and the content of register \( R3 \) is 3000. The content of each of the memory locations from 3000 to 3010 is 50. The instruction sequence starts from memory location 1000. All numbers are in decimal format and the memory is byte addressable. 
After the execution of the program, the content of memory location 3010 is \(\underline{\hspace{2cm}}\).

A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds.
The register delay between stages is 5 nanoseconds. The total time to execute 100 independent instructions is \(\underline{\hspace{2cm}}\) nanoseconds.
Consider a computer system with a byte-addressable primary memory of size \(2^{32}\) bytes.
Assume a direct-mapped cache of size 32 KB and cache block size of 64 bytes. The size of the tag field is \(\underline{\hspace{2cm}}\) bits.
Consider a pipelined processor with 5 stages: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). Each stage except EX takes one cycle. The EX stage takes one cycle for ADD and two cycles for MUL. Given the instruction sequence:
\[ \text{ADD, MUL, ADD, MUL, ADD, MUL, ADD, MUL} \] The speedup (rounded to 2 decimal places) is \(\underline{\hspace{2cm}}\).
If the numerical value of a 2-byte unsigned integer on a little endian computer is 255 more than that on a big endian computer, which of the following choices represent(s) the unsigned integer on a little endian computer?
Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements:
\[ S_1:\ \text{Read misses in a write-through L1 cache do not result in writebacks of dirty lines to the L2.} \] \[ S_2:\ \text{Write allocate policy must be used in conjunction with write-through caches and no-write allocate policy is used with writeback caches.} \] Which of the following statements is correct?
Consider a computer system with DMA support.
The DMA module transfers one 8-bit character in one CPU cycle using cycle stealing. The processor speed is 2 MHz and 0.5% of processor cycles are used for DMA. The data transfer rate of the device is \(\underline{\hspace{2cm}}\) bits per second.
Consider a set-associative cache of size 2KB with cache block size of 64 bytes. If the width of the tag field is 22 bits, the associativity of the cache is \(\underline{\hspace{2cm}}\).
Instruction format has the following structure.Instruction number OPCODE destination Source \(1\) and Source \(2\).
\(I_1:\) Div \(R_3 R_1 R_2;\)
\(I_2:\) Sub \(R_5 R_3 R_4;\)
\(I_3:\) Add \(R_3 R_5 R_6;\)
\(I_4:\) Mul \(R_7 R_3 R_8;\)