Instruction format has the following structure.Instruction number OPCODE destination Source \(1\) and Source \(2\).
\(I_1:\) Div \(R_3 R_1 R_2;\)
\(I_2:\) Sub \(R_5 R_3 R_4;\)
\(I_3:\) Add \(R_3 R_5 R_6;\)
\(I_4:\) Mul \(R_7 R_3 R_8;\)
\(I_1:\) Div \(R_3 R_1 R_2;\)
\(I_2:\) Sub \(R_5 R_3 R_4;\)
\(I_3:\) Add \(R_3 R_5 R_6;\)
\(I_4:\) Mul \(R_7 R_3 R_8;\)
There is a RAW dependency on \(R_3\) between \(I_1\) and \(I_2\)
There is a RAW dependency on \(R_3\) between \(I_2\) and \(I_3\)
There is a WAW dependency on \(R_3\) between \(I_3\) and \(I_4\)
There is a WAR dependency on \(R_3\) between \(I_1\) and \(I_3\)
The Correct Option is A, B
Solution and Explanation
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Consider the following instruction sequence where registers \( R1 \), \( R2 \), and \( R3 \) are general purpose and MEMORY[X] denotes the content at the memory location \( X \):
\[\begin{array}{|l|l|c|} \hline \textbf{Instruction} & \textbf{Semantics} & \textbf{Instruction Size (bytes)} \\ \hline \text{MOV R1, (5000)} & \text{\( R1 \leftarrow \text{MEMORY}[5000] \)} & \text{4} \\ \hline \text{MOV R2, (R3)} & \text{\( R2 \leftarrow \text{MEMORY}[R3] \)} & \text{4} \\ \hline \text{ADD R2, R1} & \text{\( R2 \leftarrow R1 + R2 \)} & \text{2} \\ \hline \text{MOV (R3), R2} & \text{\( \text{MEMORY}[R3] \leftarrow R2 \)} & \text{4} \\ \hline \text{INC R3} & \text{\( R3 \leftarrow R3 + 1 \)} & \text{2} \\ \hline \text{DEC R1} & \text{\( R1 \leftarrow R1 - 1 \)} & \text{2} \\ \hline \text{BNZ 1004} & \text{Branch if not zero to the given absolute address} & \text{2} \\ \hline \text{HALT} & \text{Stop} & \text{1} \\ \hline \end{array}\]Assume that the content of memory location 5000 is 10, and the content of register \( R3 \) is 3000. The content of each of the memory locations from 3000 to 3010 is 50. The instruction sequence starts from memory location 1000. All numbers are in decimal format and the memory is byte addressable.
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