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Telangana State Post Graduate Engineering Common Entrance Test
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Instrumentation Engineering
List of top Instrumentation Engineering Questions asked in Telangana State Post Graduate Engineering Common Entrance Test
The stack pointer in a microprocessor is a register containing:
TS PGECET - 2024
TS PGECET
Instrumentation Engineering
Microprocessors
An 8-bit microcontroller with memory map from 8000H to 9FFFH stores how many bytes?
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TS PGECET
Instrumentation Engineering
Digital Electronics and Logic Gates
In the given circuit, the race around condition:
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TS PGECET
Instrumentation Engineering
Digital Electronics and Logic Gates
Which of the following logic families has the highest fan-out?
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TS PGECET
Instrumentation Engineering
Digital Electronics and Logic Gates
Which of the following has the refreshing circuitry?
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TS PGECET
Instrumentation Engineering
Digital Electronics and Logic Gates
A 4-bit synchronous counter with series carry uses flip-flops and two AND gates with propagation delays of 30 ns and 10 ns respectively. The max time between successive clock pulses is:
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TS PGECET
Instrumentation Engineering
Digital Electronics and Logic Gates
In the JK flip-flop shown, initial Q = 0. Find output sequence at Q after each clock if \( J = K = 1 \):
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TS PGECET
Instrumentation Engineering
Digital Electronics and Logic Gates
The output \( Q_{n+1} \) of a JK flip-flop for the input \( J = 1, K = 1 \) is:
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TS PGECET
Instrumentation Engineering
Digital Electronics and Logic Gates
The binary representation of the decimal number 1.375 is:
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TS PGECET
Instrumentation Engineering
Digital Electronics and Logic Gates
The result of \( 45_{10} - 45_{16} \), expressed in 6-bit 2's complement, is:
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TS PGECET
Instrumentation Engineering
Digital Electronics and Logic Gates
The minimum number of flip-flops required to design a mod-10 counter is:
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TS PGECET
Instrumentation Engineering
Digital Electronics and Logic Gates
The expression \( a = \overline{AB} \) is equal to:
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TS PGECET
Instrumentation Engineering
Digital Electronics and Logic Gates
The combinational circuit shown uses a 4x1 multiplexer. The output \( Q \) of the circuit is:
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TS PGECET
Instrumentation Engineering
Digital Electronics and Logic Gates
For the RC circuit shown, the condition for obtaining \( \left|\frac{V_0}{V_{\text{in}}}\right| = \frac{1}{3} \) at frequency \( \omega \) rad/sec is:
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TS PGECET
Instrumentation Engineering
Analog Electronics
The OPAMP shown in the figure is:
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TS PGECET
Instrumentation Engineering
Analog Electronics
Match amplifier class with its conduction cycle:
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TS PGECET
Instrumentation Engineering
Analog Electronics
The minimal sum of products form of \( f = \overline{A}BCD + \overline{A}BCD + BCD + \overline{A}BC \) is:
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TS PGECET
Instrumentation Engineering
Digital Electronics and Logic Gates
The Boolean expression \( \overline{A + B + \overline{C}} \) is equal to:
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TS PGECET
Instrumentation Engineering
Digital Electronics and Logic Gates
A Class B push-pull complementary symmetry amplifier uses:
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Instrumentation Engineering
Power Amplifiers and 555 Timer and Voltage Regulators
An ideal op-amp has the characteristic of an ideal:
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Instrumentation Engineering
Analog Electronics
For the active filter shown, the DC gain and the 3 dB cutoff frequency are nearly: \[ C_1 = 1.0\ \text{nF},\ R_1 = 15.9\ \text{k}\Omega,\ R_2 = 159\ \text{k}\Omega \]
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TS PGECET
Instrumentation Engineering
Signals and Systems
The potential difference between the input terminals of an op-amp can be treated as nearly zero if:
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TS PGECET
Instrumentation Engineering
Analog Electronics
In a sample and hold circuit with two buffers, one at input and the other at output, the primary requirement for both buffers is:
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TS PGECET
Instrumentation Engineering
Analog Electronics
The output voltage \(V_o\) of the circuit is:
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TS PGECET
Instrumentation Engineering
Analog Electronics
The input resistance of the op-amp circuit shown is:
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TS PGECET
Instrumentation Engineering
Analog Electronics
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