Question

The synchronous sequential circuit shown below works at a clock frequency of 1 GHz. The throughput, in Mbits/s, and the latency, in ns, respectively, are 

• A. 1000, 3
• B. 333.33, 1
• C. 2000, 3
• D. 333.33, 3

Hint:

Pipeline {throughput} is limited by clock rate (one item per cycle), while {latency} equals the number of stages times the clock period.

Answer 1

The Correct Option is A

Step 1: Throughput.
A D flip-flop pipeline can accept one new input bit every clock cycle.
Clock frequency $f = 1\,\text{GHz} = 10^9\,\text{cycles/s}$.
Bits per cycle $=1 \Rightarrow$ throughput $= 1 \times 10^9\,\text{bits/s} = 1000\,\text{Mbits/s}$.
Step 2: Latency.
The data must traverse 3 cascaded DFF stages to reach the output.
Latency (in cycles) $= 3$. Each cycle is $T = 1/f = 1\,\text{ns}$.
Hence latency $= 3 \times 1\,\text{ns} = 3\,\text{ns}$.
\[ \boxed{\text{Throughput } = 1000~\text{Mbits/s}, \text{Latency } = 3~\text{ns}} \]