In the circuit shown below, P and Q are the inputs. The logical function realized by the circuit shown below is 
Step 1: Interpret the $2\times1$ MUX connections.
From the figure: $I_0$ is tied to $0$ (ground), $I_1$ is $P$, and the select input is $Q$.
Step 2: Write the MUX output equation.
For a $2\times1$ MUX, \[ Y=\overline{Q}\,I_0+Q\,I_1. \] Substitute $I_0=0$ and $I_1=P$: \[ Y=\overline{Q}. 0+Q. P=PQ. \] \[ \boxed{Y=PQ} \]
Which of the following is a functionally complete set of gates ?
(i) NAND
(ii) NOT
Here are two analogous groups, Group-I and Group-II, that list words in their decreasing order of intensity. Identify the missing word in Group-II.
Abuse \( \rightarrow \) Insult \( \rightarrow \) Ridicule
__________ \( \rightarrow \) Praise \( \rightarrow \) Appreciate
A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input \( P_0 \) is set to logic ‘0’ and \( P_1 \) is set to logic ‘1’ at all times. The timing diagram of the inputs \( SEL \) and \( S \) are also shown below. The sequence of output \( Y \) from time \( T_0 \) to \( T_3 \) is _________.

Consider a part of an electrical network as shown below. Some node voltages, and the current flowing through the \( 3\,\Omega \) resistor are as indicated.
The voltage (in Volts) at node \( X \) is _________.
