increases the number of both majority and minority charge carriers
Step 1: Reverse biasing a p-n junction diode involves connecting the p-type material to the negative terminal and the n-type material to the positive terminal of an external voltage source.
Step 2: This external reverse bias increases the width of the depletion zone as it adds to the built-in potential across the junction.
Step 3: The increased depletion zone leads to a higher potential barrier, which impedes the flow of majority carriers across the junction, effectively increasing the resistance of the diode to current flow.
Step 4: Therefore, reverse biasing increases the potential barrier, aligning with option (C).
Assuming in forward bias condition there is a voltage drop of \(0.7\) V across a silicon diode, the current through diode \(D_1\) in the circuit shown is ________ mA. (Assume all diodes in the given circuit are identical) 


For the given logic gate circuit, which of the following is the correct truth table ? 