Question

In a given sequential circuit, initial states are $Q_1=1$ and $Q_2=0$. For a clock frequency of 1 MHz, the frequency of signal $Q_2$ in kHz, is ___________ (rounded off to the nearest integer).

 

Hint:

Write next-state equations first (here \(Q_1^{+}=Q_2,\;Q_2^{+}=\overline{Q_1}\)), then walk the state sequence. Count clock steps to the first repetition to get the divide-by factor and hence the output frequency: \(f_{\text{out}}=f_{\text{clk}}/\text{(period in cycles)}\).

Answer 1

From the wiring: \(D_1 = Q_2\) and \(D_2 = \overline{Q_1}\). On each rising clock edge, \(\Rightarrow\) \[ Q_1^{+}=Q_2,\qquad Q_2^{+}=\overline{Q_1}. \] Starting with \((Q_1,Q_2)=(1,0)\): \((1,0)\Rightarrow(0,0)\Rightarrow(0,1)\Rightarrow(1,1)\Rightarrow(1,0)\Rightarrow.s\). Thus \(Q_2\) repeats every \(\mathbf{4}\) clock cycles \(\Rightarrow f_{Q_2}=f_{\text{clk}}/4=1\,\text{MHz}/4=0.25\,\text{MHz}=250\,\text{kHz\,.}\) \[ \boxed{250\ \text{kHz}} \]