Question

For the circuit shown below, the propagation delay of each NAND gate is 1 ns. The critical path delay, in ns, is ___________ (rounded off to the nearest integer). 

 

Hint:

In sequential circuits with feedback loops, like latches and flip-flops, the critical path delay is often related to the time it takes for a signal to propagate around the loop. For this cross-coupled structure, the path is through two gates.

Answer 1

Correct Answer: 2

Let the propagation delay of each NAND gate be \( t_p = 1 \, \text{ns} \).

The circuit is the familiar cross-coupled NAND latch (SR latch built from NANDs). The critical path is the longest chain of logic through which a change must propagate in order to produce a final (possibly feedback-stabilized) output change.

A useful way to identify the critical path is:
• Find an input or internal node whose change can propagate through a series of gates and then, via feedback, cause further changes until the outputs settle.
• Count the NAND stages along that longest chain (series path).

In the cross-coupled NAND latch, a typical worst-case transition involves a change that propagates through one NAND gate and then through the cross-coupled NAND driven by its output (that is, two NAND stages in series along the feedback loop). Thus, the longest combinational sequence of gate delays that must elapse before the outputs reach their new stable values is two NAND delays.

Therefore, the critical path delay is \[ T_{\text{crit}} = 2 \cdot t_p = 2 \times 1 \, \text{ns} = 2 \, \text{ns}. \]
Answer: \(\boxed{2 \, \text{ns}}\)