Question

For the circuit shown below, the propagation delay of each NAND gate is 1 ns. The critical path delay, in ns, is ___________ (rounded off to the nearest integer). 

Hint:

In cross-coupled gates, the worst-case input–output path often includes one gate plus the feedback through the second gate: count the cascaded stages and multiply by per-gate delay.

Answer 1

The diagram is a cross-coupled NAND (SR latch) with outputs \(Q\) and \(\overline{Q}\), and inputs \(A\) to the upper NAND and \(B\) to the lower NAND.
A change on \(B\) affects \(\overline{Q}\) through the lower NAND (1 ns), and that new \(\overline{Q}\) feeds back to the upper NAND to affect \(Q\) (another 1 ns).
Similarly, a change on \(A\) reaching \(\overline{Q}\) also traverses two NANDs.
Thus, the critical input–output path passes through two cascaded NAND gates.
Critical path delay \(= 2 \times 1\ \text{ns} = 2\ \text{ns}\).
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