List of top Digital Circuits Questions asked in GATE EC

A 50 $\Omega$ lossless transmission line is terminated with a load $ Z_L = (50 - j75) \, \Omega.$ { If the average incident power on the line is 10 mW, then the average power delivered to the load
(in mW, rounded off to one decimal place) is} _________.

In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns. The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is (answer in MHz).

An ideal p-n junction germanium diode has a reverse saturation current of 10 $\mu A$ at 300 K. The voltage (in Volts, rounded off to two decimal places) to be applied across the junction to get a forward bias current of 100 mA at 300 K is _________. (Consider the Boltzmann constant $ k_B = 1.38 \times 10^{-23} { J/K} $ and the charge of an electron $ e = 1.6 \times 10^{-19} { C} $.

What is the maximum frequency for Clk in MHz, given the flip-flop and logic gate delays?

An NMOS transistor operating in the linear region has $I_{DS} = 5 \, \mu{A}$ at $V_{DS} = 0.1 \, {V}$. Keeping $V_{GS}$ constant, the $V_{DS}$ is increased to $1.5 \, {V}$. Given that: \[ \mu_n C_{ox} \frac{W}{L} = 50 \, \mu{A}/{V}^2, \] the transconductance at the new operating point (in $\mu{A}/{V}$, rounded off to two decimal places) is $\_\_\_\_$.

A lossless transmission line with characteristic impedance $Z_0 = 50 \, \Omega$ is terminated with an unknown load. The magnitude of the reflection coefficient is $|\Gamma| = 0.6$. As one moves towards the generator from the load, the maximum value of the input impedance magnitude looking towards the load (in $\Omega$) is $\_\_\_\_$.

In the circuit shown below, the transistors $M_1$ and $M_2$ are biased in saturation. Their small signal transconductances are $g_{m1}$ and $g_{m2}$, respectively. Neglect body effect, channel length modulation, and intrinsic device capacitances. \begin{center} \includegraphics[width=6cm]{51.png} \end{center} Assuming that capacitor $C_1$ is a short circuit for AC analysis, the exact magnitude of small signal voltage gain $\left|\frac{v_{{out}}}{v_{{in}}}\right|$ is $\_\_\_\_$.

The sequence of states ($Q_1 Q_0$) of the given synchronous sequential circuit is $\_\_\_\_$. \begin{center} \includegraphics[width=10cm]{42.png} \end{center}

The free electron concentration profile $n(x)$ in a doped semiconductor at equilibrium is shown in the figure, where the points A, B, and C mark three different positions. Which of the following statements is/are true? \begin{center} \includegraphics[width=8cm]{26.png} \end{center}

For the circuit shown, the clock frequency is $f_0$ and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop, ________________.

Select the correct statement(s) regarding CMOS implementation of NOT gates.