Question

Select the correct statement(s) regarding CMOS implementation of NOT gates.

• A. Noise Margin High ($NM_H$) is always equal to the Noise Margin Low ($NM_L$), irrespective of transistor sizing.
• B. Dynamic power consumption during switching is zero.
• C. For a logical high input under steady state, the nMOSFET is in the linear regime of operation.
• D. Mobility of electrons never influences the switching speed of the NOT gate.

Hint:

In CMOS inverters, steady-state operation is determined by transistor regions: high input → nMOS linear, pMOS cut-off.

Answer 1

The Correct Option is C

(A) Incorrect: Noise margins depend on the voltage transfer curve (VTC), which changes with transistor sizing. Thus $NM_H \neq NM_L$ in general. (B) Incorrect: Dynamic (switching) power consumption in CMOS is: \[ P = C_L V_{DD}^2 f, \] which is non-zero because capacitors charge/discharge during switching. (C) Correct: When the input to a CMOS inverter is logic high, the nMOS gate-to-source voltage is: \[ V_{GS} = V_{DD}, \] but the drain voltage is small (near 0). Thus: \[ V_{DS} \ll V_{GS} - V_t \quad \Rightarrow \quad \text{nMOS in linear region}. \] (D) Incorrect: Electron mobility affects the nMOS drive strength, impacting switching speed. Faster electrons → faster inverter. Therefore, only (C) is correct. Final Answer: (C)