Step 1: Evaluate \( \oint_C e^z \, dz \).
The function \( e^z \) is analytic everywhere in the complex plane, including inside and on the unit circle \( C \). According to Cauchy's integral theorem, the contour integral of any analytic function over a closed curve is zero: \[ \oint_C e^z \, dz = 0. \] Step 2: Evaluate \( \oint_C z^n \, dz \).
For \( n \neq -1 \), the function \( z^n \) is analytic inside and on the unit circle. Hence, by Cauchy's theorem, the integral is zero: \[ \oint_C z^n \, dz = 0 \quad {(for \( n \neq -1 \))}. \] Since the question specifies \( n \) as an even integer, it satisfies the condition for \( n \neq -1 \).
Step 3: Evaluate \( \oint_C \cos z \, dz \).
The function \( \cos z \) is analytic everywhere, so its contour integral over the unit circle is zero: \[ \oint_C \cos z \, dz = 0. \] Step 4: Evaluate \( \oint_C \sec z \, dz \).
The function \( \sec z \) has singularities at odd multiples of \( \pi/2 \), so it does not satisfy the conditions of Cauchy's theorem and the integral does not vanish: \[ \oint_C \sec z \, dz \neq 0. \] Thus, the correct answers are (A) and (B).
Here are two analogous groups, Group-I and Group-II, that list words in their decreasing order of intensity. Identify the missing word in Group-II.
Abuse \( \rightarrow \) Insult \( \rightarrow \) Ridicule
__________ \( \rightarrow \) Praise \( \rightarrow \) Appreciate
Two resistors are connected in a circuit loop of area 5 m\(^2\), as shown in the figure below. The circuit loop is placed on the \( x-y \) plane. When a time-varying magnetic flux, with flux-density \( B(t) = 0.5t \) (in Tesla), is applied along the positive \( z \)-axis, the magnitude of current \( I \) (in Amperes, rounded off to two decimal places) in the loop is (answer in Amperes).
A 50 \(\Omega\) lossless transmission line is terminated with a load \( Z_L = (50 - j75) \, \Omega.\) { If the average incident power on the line is 10 mW, then the average power delivered to the load
(in mW, rounded off to one decimal place) is} _________.
In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns. The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is (answer in MHz).