The \( Z \)-parameter matrix of a two-port network relates the port voltages and port currents as follows: \[ \begin{bmatrix} V_1 \\ V_2 \end{bmatrix} = Z \begin{bmatrix} I_1 \\ I_2 \end{bmatrix} \] The \( Z \)-parameter matrix (with each entry in Ohms) of the network shown below is _________.
In a weighted-resistor DAC, each input bit corresponds to a weighted resistor, with each switch closing when the corresponding input bit is '1'. The output voltage is calculated using the resistor network, where the voltages are summed according to the weights of the resistors. The resistor values corresponding to the inputs \( b_3, b_2, b_1, \) and \( b_0 \) are \( 2R, R, 4R, 8R \) respectively.
Step 1: Find the output voltage for input \( b_3b_2b_1b_0 = 1110 \)
For the input \( b_3b_2b_1b_0 = 1110 \), the switches corresponding to \( b_3, b_2, b_1 \) are closed, and the switch corresponding to \( b_0 \) is open. The weighted resistors are \( 2R, R, 4R, 8R \). The output voltage \( V_o \) is given by the formula: \[ V_o = V_{{REF}} \left( \frac{b_3}{2^3} + \frac{b_2}{2^2} + \frac{b_1}{2^1} + \frac{b_0}{2^0} \right) \] For \( b_3b_2b_1b_0 = 1110 \), we substitute the values: \[ V_o = 2 \left( \frac{1}{2^3} + \frac{1}{2^2} + \frac{1}{2^1} + 0 \right) \] \[ V_o = 2 \left( \frac{1}{8} + \frac{1}{4} + \frac{1}{2} \right) \] \[ V_o = 2 \left( \frac{1}{8} + \frac{2}{8} + \frac{4}{8} \right) = 2 \times \frac{7}{8} = \frac{7}{4} = 1.75 \, {V} = 1750 \, {mV}. \] Step 2: Find the output voltage for input \( b_3b_2b_1b_0 = 1101 \)
For the input \( b_3b_2b_1b_0 = 1101 \), the switches corresponding to \( b_3, b_2, b_0 \) are closed, and the switch corresponding to \( b_1 \) is open. The weighted resistors are \( 2R, R, 4R, 8R \). The output voltage \( V_o \) is given by: \[ V_o = V_{{REF}} \left( \frac{b_3}{2^3} + \frac{b_2}{2^2} + \frac{b_1}{2^1} + \frac{b_0}{2^0} \right) \] For \( b_3b_2b_1b_0 = 1101 \), we substitute the values: \[ V_o = 2 \left( \frac{1}{2^3} + \frac{1}{2^2} + 0 + \frac{1}{2^0} \right) \] \[ V_o = 2 \left( \frac{1}{8} + \frac{1}{4} + 0 + 1 \right) \] \[ V_o = 2 \left( \frac{1}{8} + \frac{2}{8} + \frac{8}{8} \right) = 2 \times \frac{11}{8} = \frac{11}{4} = 2.75 \, {V} = 2750 \, {mV}. \] Step 3: Calculate the change in output voltage
The change in output voltage is given by: \[ \Delta V_o = 2750 \, {mV} - 1750 \, {mV} = 1000 \, {mV}. \] Thus, the magnitude of the change in output voltage is 250 mV (rounded to nearest integer).
Let \( G(s) = \frac{1}{10s^2} \) be the transfer function of a second-order system. A controller \( M(s) \) is connected to the system \( G(s) \) in the configuration shown below.
Consider the following statements.
Which one of the following options is correct?
A 4-bit weighted-resistor DAC with inputs \( b_3, b_2, b_1, \) and \( b_0 \) (MSB to LSB) is designed using an ideal opamp, as shown below. The switches are closed when the corresponding input bits are logic ‘1’ and open otherwise. When the input \( b_3b_2b_1b_0 \) changes from 1110 to 1101, the magnitude of the change in the output voltage \( V_o \) (in mV, rounded off to the nearest integer) is _________.
Two resistors are connected in a circuit loop of area 5 m\(^2\), as shown in the figure below. The circuit loop is placed on the \( x-y \) plane. When a time-varying magnetic flux, with flux-density \( B(t) = 0.5t \) (in Tesla), is applied along the positive \( z \)-axis, the magnitude of current \( I \) (in Amperes, rounded off to two decimal places) in the loop is (answer in Amperes).
A 50 \(\Omega\) lossless transmission line is terminated with a load \( Z_L = (50 - j75) \, \Omega.\) { If the average incident power on the line is 10 mW, then the average power delivered to the load
(in mW, rounded off to one decimal place) is} _________.
In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns. The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is (answer in MHz).
The diode in the circuit shown below is ideal. The input voltage (in Volts) is given by \[ V_I = 10 \sin(100\pi t), \quad {where time} \, t \, {is in seconds.} \] The time duration (in ms, rounded off to two decimal places) for which the diode is forward biased during one period of the input is (answer in ms).