A 4-bit weighted-resistor DAC with inputs \( b_3, b_2, b_1, \) and \( b_0 \) (MSB to LSB) is designed using an ideal opamp, as shown below. The switches are closed when the corresponding input bits are logic ‘1’ and open otherwise. When the input \( b_3b_2b_1b_0 \) changes from 1110 to 1101, the magnitude of the change in the output voltage \( V_o \) (in mV, rounded off to the nearest integer) is _________.
