An OR gate gives a high output (logic 1) if any one or both of its inputs are high.
The only time an OR gate outputs low (logic 0) is when both inputs are low.
Truth table for a two-input OR gate:
Match the LIST-I with LIST-II
LIST-I (Logic Gates) | LIST-II (Expressions) | ||
---|---|---|---|
A. | EX-OR | I. | \( A\bar{B} + \bar{A}B \) |
B. | NAND | II. | \( A + B \) |
C. | OR | III. | \( AB \) |
D. | EX-NOR | IV. | \( \bar{A}\bar{B} + AB \) |
Choose the correct answer from the options given below:
Match List-I with List-II:
List-I (Counters) | List-II (Delay/Number of States) |
---|---|
(A) n-bit ring counter | (I) Number of states is \( 2^n \) |
(B) MOD-\(2^n\) asynchronous counter | (II) Fastest counter |
(C) n-bit Johnson counter | (III) Number of used states is \( n \) |
(D) Synchronous counter | (IV) Number of used states is \( 2n \) |
Choose the correct answer from the options given below:
A MOD 2 and a MOD 5 up-counter when cascaded together results in a MOD ______ counter.
If 0.01 mol of $\mathrm{P_4O_{10}}$ is removed from 0.1 mol, then the remaining molecules of $\mathrm{P_4O_{10}}$ will be: