The identical MOSFETs \( M_1 \) and \( M_2 \) in the circuit given below are ideal and biased in the saturation region. \( M_1 \) and \( M_2 \) have a transconductance \( g_m \) of 5 mS. The input signals (in Volts) are: \[ V_1 = 2.5 + 0.01 \sin \omega t, \quad V_2 = 2.5 - 0.01 \sin \omega t. \] The output signal \( V_3 \) (in Volts) is _________.

Step 1: Identify the type of circuit and signal behavior.
We are given a circuit with two MOSFETs \( M_1 \) and \( M_2 \), both of which are biased in the saturation region. The transconductance \( g_m = 5 \, {mS} \) indicates that each MOSFET operates as a current amplifier.
Step 2: Use the input voltages.
The input voltages are given as: \[ V_1 = 2.5 + 0.01 \sin \omega t, \quad V_2 = 2.5 - 0.01 \sin \omega t. \] These voltages are in the form of a DC value with a small AC perturbation.
Step 3: Calculate the output of the MOSFETs.
Each MOSFET's drain current is proportional to the voltage difference between the gate and the source, which is controlled by the input voltage. Given the small signal behavior, we calculate the small signal drain currents as: \[ I_{D1} = g_m \cdot (V_1 - V_{{bias}}), \quad I_{D2} = g_m \cdot (V_2 - V_{{bias}}), \] where \( V_{{bias}} = 2.5 \, {V} \) is the bias voltage for both MOSFETs. For small signal calculations: \[ I_{D1} = g_m \cdot (0.01 \sin \omega t), \quad I_{D2} = g_m \cdot (-0.01 \sin \omega t). \] Thus, the total current flowing through the resistive load will be: \[ I_{{total}} = I_{D1} + I_{D2} = 5 \, {mS} \cdot 0.01 \sin \omega t - 5 \, {mS} \cdot 0.01 \sin \omega t = 0. \] This indicates that the currents through the two MOSFETs cancel each other out at the signal frequency.
Step 4: Apply the voltage across the resistor.
The resistor values are \( 1\,{k}\Omega \), and the output voltage \( V_3 \) is determined by the current through this resistor. Considering that the currents are small signal and their net effect is subtracted, the output voltage will be: \[ V_3 = V_{{bias}} + \Delta V = 4 - 0.05 \sin(\omega t) \] Therefore, the output voltage \( V_3 \) is \( 4 - 0.05 \sin \omega t \), and the correct answer is (D).
A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input \( P_0 \) is set to logic ‘0’ and \( P_1 \) is set to logic ‘1’ at all times. The timing diagram of the inputs \( SEL \) and \( S \) are also shown below. The sequence of output \( Y \) from time \( T_0 \) to \( T_3 \) is _________.

Consider a part of an electrical network as shown below. Some node voltages, and the current flowing through the \( 3\,\Omega \) resistor are as indicated.
The voltage (in Volts) at node \( X \) is _________.

The 12 musical notes are given as \( C, C^\#, D, D^\#, E, F, F^\#, G, G^\#, A, A^\#, B \). Frequency of each note is \( \sqrt[12]{2} \) times the frequency of the previous note. If the frequency of the note C is 130.8 Hz, then the ratio of frequencies of notes F# and C is:
A 4-bit weighted-resistor DAC with inputs \( b_3, b_2, b_1, \) and \( b_0 \) (MSB to LSB) is designed using an ideal opamp, as shown below. The switches are closed when the corresponding input bits are logic ‘1’ and open otherwise. When the input \( b_3b_2b_1b_0 \) changes from 1110 to 1101, the magnitude of the change in the output voltage \( V_o \) (in mV, rounded off to the nearest integer) is _________.
