The identical MOSFETs \( M_1 \) and \( M_2 \) in the circuit given below are ideal and biased in the saturation region. \( M_1 \) and \( M_2 \) have a transconductance \( g_m \) of 5 mS. The input signals (in Volts) are: \[ V_1 = 2.5 + 0.01 \sin \omega t, \quad V_2 = 2.5 - 0.01 \sin \omega t. \] The output signal \( V_3 \) (in Volts) is _________.
Step 1: Identify the type of circuit and signal behavior.
We are given a circuit with two MOSFETs \( M_1 \) and \( M_2 \), both of which are biased in the saturation region. The transconductance \( g_m = 5 \, {mS} \) indicates that each MOSFET operates as a current amplifier.
Step 2: Use the input voltages.
The input voltages are given as: \[ V_1 = 2.5 + 0.01 \sin \omega t, \quad V_2 = 2.5 - 0.01 \sin \omega t. \] These voltages are in the form of a DC value with a small AC perturbation.
Step 3: Calculate the output of the MOSFETs.
Each MOSFET's drain current is proportional to the voltage difference between the gate and the source, which is controlled by the input voltage. Given the small signal behavior, we calculate the small signal drain currents as: \[ I_{D1} = g_m \cdot (V_1 - V_{{bias}}), \quad I_{D2} = g_m \cdot (V_2 - V_{{bias}}), \] where \( V_{{bias}} = 2.5 \, {V} \) is the bias voltage for both MOSFETs. For small signal calculations: \[ I_{D1} = g_m \cdot (0.01 \sin \omega t), \quad I_{D2} = g_m \cdot (-0.01 \sin \omega t). \] Thus, the total current flowing through the resistive load will be: \[ I_{{total}} = I_{D1} + I_{D2} = 5 \, {mS} \cdot 0.01 \sin \omega t - 5 \, {mS} \cdot 0.01 \sin \omega t = 0. \] This indicates that the currents through the two MOSFETs cancel each other out at the signal frequency.
Step 4: Apply the voltage across the resistor.
The resistor values are \( 1\,{k}\Omega \), and the output voltage \( V_3 \) is determined by the current through this resistor. Considering that the currents are small signal and their net effect is subtracted, the output voltage will be: \[ V_3 = V_{{bias}} + \Delta V = 4 - 0.05 \sin(\omega t) \] Therefore, the output voltage \( V_3 \) is \( 4 - 0.05 \sin \omega t \), and the correct answer is (D).
A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input \( P_0 \) is set to logic ‘0’ and \( P_1 \) is set to logic ‘1’ at all times. The timing diagram of the inputs \( SEL \) and \( S \) are also shown below. The sequence of output \( Y \) from time \( T_0 \) to \( T_3 \) is _________.
Two resistors are connected in a circuit loop of area 5 m\(^2\), as shown in the figure below. The circuit loop is placed on the \( x-y \) plane. When a time-varying magnetic flux, with flux-density \( B(t) = 0.5t \) (in Tesla), is applied along the positive \( z \)-axis, the magnitude of current \( I \) (in Amperes, rounded off to two decimal places) in the loop is (answer in Amperes).
A 50 \(\Omega\) lossless transmission line is terminated with a load \( Z_L = (50 - j75) \, \Omega.\) { If the average incident power on the line is 10 mW, then the average power delivered to the load
(in mW, rounded off to one decimal place) is} _________.
In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns. The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is (answer in MHz).
The diode in the circuit shown below is ideal. The input voltage (in Volts) is given by \[ V_I = 10 \sin(100\pi t), \quad {where time} \, t \, {is in seconds.} \] The time duration (in ms, rounded off to two decimal places) for which the diode is forward biased during one period of the input is (answer in ms).