In the circuit shown, the identical transistors Q1 and Q2 are biased in the active region with \( \beta = 120 \). The Zener diode is in the breakdown region with \( V_Z = 5 \, V \) and \( I_Z = 25 \, mA \). If \( I_L = 12 \, mA \) and \( V_{EB1} = V_{EB2} = 0.7 \, V \), then the values of \( R_1 \) and \( R_2 \) (in \( k\Omega \), rounded off to one decimal place) are _________, respectively.
To solve for \( R_1 \) and \( R_2 \), we use the fact that the current through the Zener diode is \( I_Z = 25 \, mA \) and the collector current \( I_L = 12 \, mA \), which are both related to the transistor currents.
Step 1: Apply KVL for the collector loop:
The voltage across \( R_2 \) is: \[ V_{R2} = I_L R_2 \] From the circuit, we know: \[ V_{CC} = 20 \, V, \quad V_{EB1} = 0.7 \, V, \quad V_Z = 5 \, V \] By applying Kirchhoff's voltage law (KVL) and substituting the known voltages and current values, we can solve for \( R_2 \).
Step 2: Apply KVL for the base loop:
Similarly, for \( R_1 \), we can calculate using KVL. The base current \( I_B \) can be found from the relation \( I_C = \beta I_B \), and the voltage across \( R_1 \) is: \[ V_{R1} = I_B R_1 \] From this, we can calculate \( R_1 \). After solving these equations using the given values, we find: \[ R_1 = 0.6 \, k\Omega \quad {and} \quad R_2 = 0.4 \, k\Omega. \] Thus, the correct answer is (A): \( R_1 = 0.6 \, k\Omega \) and \( R_2 = 0.4 \, k\Omega \).
Two resistors are connected in a circuit loop of area 5 m\(^2\), as shown in the figure below. The circuit loop is placed on the \( x-y \) plane. When a time-varying magnetic flux, with flux-density \( B(t) = 0.5t \) (in Tesla), is applied along the positive \( z \)-axis, the magnitude of current \( I \) (in Amperes, rounded off to two decimal places) in the loop is (answer in Amperes).
A 50 \(\Omega\) lossless transmission line is terminated with a load \( Z_L = (50 - j75) \, \Omega.\) { If the average incident power on the line is 10 mW, then the average power delivered to the load
(in mW, rounded off to one decimal place) is} _________.
In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns. The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is (answer in MHz).
The diode in the circuit shown below is ideal. The input voltage (in Volts) is given by \[ V_I = 10 \sin(100\pi t), \quad {where time} \, t \, {is in seconds.} \] The time duration (in ms, rounded off to two decimal places) for which the diode is forward biased during one period of the input is (answer in ms).