A JK flip-flop has inputs $J = 1$ and $K = 1$.
The clock input is applied as shown. Find the output clock cycles per second (output frequency).

In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns. The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is (answer in MHz).

A 50 \(\Omega\) lossless transmission line is terminated with a load \( Z_L = (50 - j75) \, \Omega.\) { If the average incident power on the line is 10 mW, then the average power delivered to the load
(in mW, rounded off to one decimal place) is} _________.
In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns. The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is (answer in MHz).
f(w, x, y, z) =\( \Sigma\) (0, 2, 5, 7, 8, 10, 13, 14, 15)
Find the correct simplified expression.
For the non-inverting amplifier shown in the figure, the input voltage is 1 V. The feedback network consists of 2 k$\Omega$ and 1 k$\Omega$ resistors as shown.
If the switch is open, $V_o = x$.
If the switch is closed, $V_o = ____ x$.

Consider the system described by the difference equation
\[ y(n) = \frac{5}{6}y(n-1) - \frac{1}{6}(4-n) + x(n). \] Determine whether the system is linear and time-invariant (LTI).
Find the area of the square shown in the figure whose vertices are at $(0,0)$, $(1,1)$, $(2,0)$ and $(1,-1)$.
