

The circuit shown in figure is
For the circuit shown in the figure, the delay of the bubbled NAND gate is 5 ns and that of the counter is assumed to be zero. If the clock (Clk) frequency is 12 MHz, then the counter behaves as a ________.
If A + B means A is the mother of B; A - B means A is the brother of B; A % B means A is the father of B, and A \(\times\) B means A is the sister of B, which of the following shows that P is the maternal uncle of Q?