Parity checking is an error detection technique that verifies whether the number of '1' bits in a set of bits is even or odd
Parity generator circuits (which add the parity bit) and parity checker circuits (which verify the parity) are built using Exclusive-OR (XOR) gates
The property of the XOR gate is that its output is '1' if there is an odd number of '1's at its inputs, and '0' if there is an even number of '1's
By cascading XOR gates for all the data bits (and the parity bit in the checker), the final output indicates the overall parity or signals an error if the received parity doesn't match the expected parity scheme (even or odd)