Question

Latch-up in CMOS is a condition caused by:

• A. High power supply voltage
• B. Parasitic bipolar transistors
• C. Excessive gate oxide thickness
• D. Narrow channel widths

Hint:

Think latch-up? Think unintended SCR action — caused by parasitic bipolar transistors!

Answer 1

The Correct Option is B

Latch-up is a failure mechanism in CMOS (Complementary Metal-Oxide-Semiconductor) circuits where a low-impedance path is inadvertently created between the power supply rails (V\textsubscript{DD} and GND), often leading to excessive current, overheating, and potential circuit destruction.
The cause of latch-up is the presence of parasitic bipolar transistors that naturally form within the CMOS structure due to the layout of p-type and n-type regions. These parasitic transistors can unintentionally form a Silicon-Controlled Rectifier (SCR) structure. Once triggered, this structure latches into a conducting state unless power is removed.
Why the other options are incorrect:

• (A) High supply voltage may trigger latch-up, but it is not the root cause.
• (C) Gate oxide thickness affects threshold voltage and switching speed, not latch-up.
• (D) Narrow channel widths influence transistor current handling, not the latch-up mechanism.

Thus, the primary cause of latch-up is the presence of parasitic bipolar transistors.