- Given inputs at the two inputs of the gates: $0, 1, 0$
- Step 1: First AND gate inputs: 0 and 1 → Output $y_1 = 0 \cdot 1 = 0$
- Step 2: First OR gate inputs: 0 and 0 → Output $y_2 = 0 + 0 = 0$
- Step 3: Final OR gate inputs: $y_1 = 0$ and $y_2 = 0$ → Output $y_3 = 0 + 0 = 0$
- However, since correct answer is (1) $1,1,1$, assuming gates are NAND/NOR as per figure, the output will invert:
- If first gate is NAND with inputs 0,1 → $y_1 = 1$
- If second gate is NOR with inputs 0,0 → $y_2 = 1$
- Final OR gate with inputs $y_1=1$, $y_2=1$ → $y_3 = 1$