The circuit shown in figure is
For the circuit shown in the figure, the delay of the bubbled NAND gate is 5 ns and that of the counter is assumed to be zero. If the clock (Clk) frequency is 12 MHz, then the counter behaves as a ________.
The circuit shown in the figure can be used as a ________.
If diode cut-in voltage is 0.6 V. The diode status are