


The circuit shown in figure is
For the circuit shown in the figure, the delay of the bubbled NAND gate is 5 ns and that of the counter is assumed to be zero. If the clock (Clk) frequency is 12 MHz, then the counter behaves as a ________.
The following figures show three curves generated using an iterative algorithm. The total length of the curve generated after 'Iteration n' is:

Consider the unity-negative-feedback system shown in Figure (i) below, where gain \( K \geq 0 \). The root locus of this system is shown in Figure (ii) below.
For what value(s) of \( K \) will the system in Figure (i) have a pole at \( -1 + j1 \)?
