Consider the unity-negative-feedback system shown in Figure (i) below, where gain \( K \geq 0 \). The root locus of this system is shown in Figure (ii) below.
For what value(s) of \( K \) will the system in Figure (i) have a pole at \( -1 + j1 \)?
A feedback control system is shown in the figure.
The maximum allowable value of \( n \) such that the output \( y(t) \), due to any step disturbance signal \( d(t) \), becomes zero at steady-state, is ________ (in integer).
The plant in the feedback control system shown in the figure is \( P(s) = \frac{a}{s^2 - b^2} \), where \( a > 0 \) and \( b > 0 \). The type(s) of controller \( C(s) \) that CANNOT stabilize the plant is/are
Consider the control system block diagram given in Figure (a). The loop transfer function $G(s)H(s)$ does not have any pole on the $j\omega$-axis. The counterclockwise contour with infinite radius, as shown in Figure (b), encircles two poles of $G(s)H(s)$. Choose the correct statement from the following options for closed loop stability of the system.
Here are two analogous groups, Group-I and Group-II, that list words in their decreasing order of intensity. Identify the missing word in Group-II.
Abuse \( \rightarrow \) Insult \( \rightarrow \) Ridicule
__________ \( \rightarrow \) Praise \( \rightarrow \) Appreciate
Two resistors are connected in a circuit loop of area 5 m\(^2\), as shown in the figure below. The circuit loop is placed on the \( x-y \) plane. When a time-varying magnetic flux, with flux-density \( B(t) = 0.5t \) (in Tesla), is applied along the positive \( z \)-axis, the magnitude of current \( I \) (in Amperes, rounded off to two decimal places) in the loop is (answer in Amperes).
A 50 \(\Omega\) lossless transmission line is terminated with a load \( Z_L = (50 - j75) \, \Omega.\) { If the average incident power on the line is 10 mW, then the average power delivered to the load
(in mW, rounded off to one decimal place) is} _________.
In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns. The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is (answer in MHz).