Most microcontrollers implement a prioritized interrupt system
When an interrupt occurs, the microcontroller typically disables further interrupts (or at least interrupts of the same or lower priority) while it is servicing the current one (executing the Interrupt Service Routine - ISR)
However, if a *higher priority* interrupt occurs while a lower priority interrupt is being serviced, the microcontroller usually:
(1) Completes the current instruction of the lower priority ISR
(2) Saves the context of the lower priority ISR
(3) Jumps to and executes the ISR for the new, higher priority interrupt
(4) Upon completion of the higher priority ISR, it restores the context and resumes the lower priority ISR
Interrupts of lower or equal priority occurring during an ISR are typically ignored or held pending until the current ISR completes and interrupts are re-enabled
Simultaneous handling is generally not possible in single-core controllers
Option (1) correctly describes the principle of prioritized interrupts, where a higher priority interrupt can preempt a lower priority one
The interrupt vector table helps locate the ISR, and priority levels are associated with different interrupt sources