The given two-port network is a symmetric T-network with series arms \(Z_1 = 1\Omega\), \(Z_3 = 1\Omega\) and shunt arm \(Z_2 = 4\Omega\).
ABCD parameters for a T-network:
\(A = 1 + \frac{Z_1}{Z_2}\)
\(B = Z_1 + Z_3 + \frac{Z_1 Z_3}{Z_2}\)
\(C = \frac{1}{Z_2}\)
\(D = 1 + \frac{Z_3}{Z_2}\)
Here, \(Z_1 = 1\Omega\), \(Z_2 = 4\Omega\), \(Z_3 = 1\Omega\).
B =
\(1 + 1 + \frac{1 \times 1}{4} = 2 + \frac{1}{4} = \frac{8+1}{4} = \frac{9}{4} \Omega\)
D =
\(1 + \frac{1}{4} = \frac{4+1}{4} = \frac{5}{4}\) (dimensionless)
\[ \boxed{\text{B = 9/4, D = 5/4}} \]
The bus impedance matrix of a 4-bus power system is given.
A branch having an impedance of \( j0.2 \Omega \) is connected between bus 2 and the reference. Then the values of \( Z_{22,new} \) and \( Z_{23,new} \) of the bus impedance matrix of the modified network are respectively _______.
When the input to Q is a 1 level, the frequency of oscillations of the timer circuit is _______.
The logic circuit given below converts a binary code \(Y_1, Y_2, Y_3\) into _______.
The bus admittance matrix of the network shown in the given figure, for which the marked parameters are per unit impedance, is _______.