Question

The following circuit employing pass transistor logic, all NMOS transistors are identical with a threshold voltage of 1 V. Ignoring the body-effect, the output voltages at P, Q and R are,

• A. 4V, 4V, 4V
• B. 4V, 3V, 2V
• C. 5V, 5V, 5V
• D. 5V, 4V, 3V

Hint:

For an NMOS pass transistor with its gate tied to VDD, the maximum output high voltage (\(V_{OH}\)) is \(VDD - V_{th}\). In a chain, this drop only occurs at the first stage if the body effect is ignored. Subsequent stages will pass this already-dropped voltage without further degradation.

Answer 1

The Correct Option is A

Step 1: Analyze the first transistor (output at P). This is an NMOS pass transistor. An NMOS transistor passes a strong '0' but a weak '1'. The highest voltage it can pass is limited by its gate voltage and threshold voltage. The input to the drain is 5V. The gate voltage is 5V. The output is at the source, Vp. The transistor will stop conducting when its source voltage rises to the point where \(V_{GS} = V_{th}\). \[ V_G - V_S = V_{th} \] \[ 5V - V_p = 1V \implies V_p = 4V \] So, the output voltage at P is 4V.
Step 2: Analyze the second transistor (output at Q). The input to the drain of this transistor is the output from the previous stage, \(V_p = 4V\). The gate voltage is still 5V. The output is Vq. The maximum possible output is again limited by \(V_G - V_{th} = 5V - 1V = 4V\). Since the input to this stage (at the drain) is only 4V, the source voltage cannot rise above 4V. The transistor will conduct as long as \(V_{GS}>V_{th}\) (i.e., \(5V - V_q>1V\)) and there is a voltage difference across it (\(V_{DS}>0\)). As Vq approaches 4V, \(V_{DS} = V_p - V_q\) approaches 0, and current stops flowing. Thus, Vq will settle at 4V.
Step 3: Analyze the third transistor (output at R). The logic is identical to Step 2. The input to the drain is \(V_q = 4V\). The gate is at 5V. The maximum possible output is \(V_G - V_{th} = 4V\). The output Vr will therefore also be 4V. Since the question specifies to ignore the body effect, the threshold voltage remains 1V for all transistors, and the voltage does not degrade past the first stage. The outputs are (4V, 4V, 4V).