Suppose we are transmitting frames between two nodes using the Stop-and-Wait protocol. The frame size is 3000 bits. The transmission rate of the channel is 2000 bps (bits/second) and the propagation delay between the two nodes is 100 milliseconds. Assume that the processing times at the source and destination are negligible. Also, assume that the size of the acknowledgement packet is negligible. Which ONE of the following most accurately gives the channel utilization for the above scenario in percentage?
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- 88.23
- 93.75
- 85.44
- 66.67
The Correct Option is A
Solution and Explanation
Top Questions on Operating Systems
- A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is ___________ . (rounded off to two decimal places)
- GATE CS - 2025
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- Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the “hit rate” for L1 cache is 90% while the processor is accessing the data from L1 cache. Whereas, for the second level (L2) cache, the “hit rate” is 80% and the “miss penalty” for transferring data from L2 cache to L1 cache is 10 ns. The “miss penalty” for the data to be transferred from main memory to L2 cache is 100 ns. Then the average memory access time in this system in nanoseconds is ___________ . (rounded off to one decimal place)
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Consider a system with the following: - \(\mathbb{P} = \{ P_1, P_2, P_3, P_4 \}\) consists of all active processes in an operating system. - \(\mathbb{R} = \{ R_1, R_2, R_3, R_4 \}\) consists of single instances of distinct types of resources in the system.
The resource allocation graph has the following assignment and claim edges: Assignment edges: \[ R_1 \to P_1, \quad R_2 \to P_2, \quad R_3 \to P_3, \quad R_4 \to P_4 \] (The assignment edge \( R_1 \to P_1 \) means resource \( R_1 \) is assigned to process \( P_1 \), and so on for others.)
Claim edges: \[ P_1 \to R_2, \quad P_2 \to R_3, \quad P_3 \to R_1, \quad P_2 \to R_4, \quad P_4 \to R_2 \] (The claim edge \( P_1 \to R_2 \) means process \( P_1 \) is waiting for resource \( R_2 \), and so on for others.)
Which of the following statement(s) is/are CORRECT?- GATE CS - 2025
- Computer Science and IT Engineering
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- Which of the following is/are part of an Instruction Set Architecture of a processor?
- GATE CS - 2025
- Computer Science and IT Engineering
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Questions Asked in GATE CS exam
The unit interval \((0, 1)\) is divided at a point chosen uniformly distributed over \((0, 1)\) in \(\mathbb{R}\) into two disjoint subintervals. The expected length of the subinterval that contains 0.4 is ___________. (rounded off to two decimal places)
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- Calculus
A quadratic polynomial \( (x - \alpha)(x - \beta) \) over complex numbers is said to be square invariant if \[ (x - \alpha)(x - \beta) = (x - \alpha^2)(x - \beta^2). \] Suppose from the set of all square invariant quadratic polynomials we choose one at random. The probability that the roots of the chosen polynomial are equal is ___________. (rounded off to one decimal place)
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Consider the following C program:
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Consider the following C program:
The output of the above program is __________ . (Answer in integer)
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An application executes \( 6.4 \times 10^8 \) number of instructions in 6.3 seconds. There are four types of instructions, the details of which are given in the table. The duration of a clock cycle in nanoseconds is ____________. (rounded off to one decimal place)
