Question

On execution of the program segment: 

• A. RST 6.5 is disabled, but other interrupts are enable(D)
• B. RST 7.5 is disabled, but other interrupts are enable(D)
• C. RST 5.5 is disabled, but other interrupts are enable(D)
• D. Both RST 5.5 and RST 6.5 are disabled, but other interrupts are enable(D)

Hint:

The SIM instruction in 8085 controls interrupt masking. When MVI A, 0Ah is executed, only RST 5.5 is disabled, while other interrupts remain enable(D).

Answer 1

The Correct Option is C

Step 1: The SIM (Set Interrupt Mask) instruction in 8085 is used to control maskable interrupts using the Accumulator (A). 
Step 2: The bit pattern of Accumulator A determines which interrupts are enabled or disabled: \[ \text{D7} \quad \text{D6} \quad \text{D5} \quad \text{D4} \quad \text{D3} \quad \text{D2} \quad \text{D1} \quad \text{D0} \] \[ \quad SOD \quad \quad \text{X} \quad \quad \text{R7.5} \quad \quad MSE \quad \quad M75 \quad \quad M65 \quad \quad M55 \] where:
- D3 (MSE - Mask Set Enable) enables the mask settings.
- D2 (M75) masks RST 7.5.
- D1 (M65) masks RST 6.5.
- D0 (M55) masks RST 5.5. 
Step 3: The given instruction: \[ MVI A, 0Ah = 0000\ 1010_2 \] - \( D3 = 1 \) → Masking enable(D)
- \( D1 = 0 \) → RST 6.5 not masked (enabled).
- \( D0 = 1 \) → RST 5.5 masked (disabled).
Step 4: Evaluating options: 
- (A) Incorrect: RST 6.5 is enable(D) 
- (B) Incorrect: RST 7.5 is not affected 
- (C) Correct: RST 5.5 is disabled, but other interrupts are enable(D) 
- (D) Incorrect: RST 6.5 is not disabled