Question

Figure shows a circuit diagram comprising Boolean logic gates and the corresponding timing diagrams showing digital signals at various points in the circuit. Which of the following is/are true? 

• A. Points 3 and 7 are shorted.
• B. The NOT gate on the right is faulty.
• C. The AND gate is faulty and acts like a NOR gate.
• D. The NAND gate is faulty and acts like an OR gate.

Hint:

In timing analysis of logic circuits, compare truth table outputs with observed waveforms to identify faulty gates.

Answer 1

The Correct Option is D

Step 1: Analyze circuit behavior.
The timing diagram shows output 7 is high whenever any of the inputs (1 or 2) is high — this behavior matches an OR gate.

Step 2: Compare with given circuit.
Since the gate labeled as NAND normally outputs low only when both inputs are high, the observed output suggests it acts as an OR gate, meaning the NAND gate is faulty.

Step 3: Verify other possibilities.
- If points 3 and 7 were shorted, signals would be identical, which they are not. - The NOT gate and AND gate behave as expected per waveforms.

Step 4: Conclusion.
Hence, the NAND gate is faulty and behaves like an OR gate.