Question

Consider a 3-stage pipelined processor having a delay of 10 ns, 20 ns, and 14 ns for the first, second, and third stages, respectively. Assume that there is no other delay and the processor does not suffer from any pipeline hazards. Also assume that one instruction is fetched every cycle.
The total execution time for executing 100 instructions on this processor is ________ ns.

Hint:

For an ideal $k$-stage pipeline with no hazards and negligible latch overhead: $T=(k+N-1)\times \max\{\text{stage delays}\}$. The first instruction takes $kT_c$; each subsequent one completes every $T_c$.

Answer 1

Step 1: Determine pipeline clock period.
The cycle time of a synchronous pipeline is set by the slowest stage.
Given stage delays: $10$ ns, $20$ ns, $14$ ns $\Rightarrow$ clock period $T_c=\max(10,20,14)=20$ ns.
Step 2: Compute total time for $N$ instructions in a $k$-stage pipeline.
Total time $T = (k + N - 1)\,T_c$, where $k=3$ stages and $N=100$ instructions.
So, $T=(3+100-1)\times 20=(102)\times 20=2040$ ns.
\[ \boxed{T=2040~\text{ns}} \]