An 8-bit microprocessor has a 16-bit address bus ($A_{15} - A_0$) where $A_0$ is the LSB. As shown in Figure (a), it has a pre-installed 4 KB ROM whose starting address is 0000 H. The processor needs to be upgraded by adding a 16 KB RAM as shown in Figure (b). The address range for the newly added RAM is
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Carefully analyze the chip select logic. The memory chip is selected when its chip select pin is active. Map the address bits to the chip select logic to determine the address range for which the memory is enabled.
Step 1: Analyze the chip select logic for the RAM.
The chip select for the 16 KB RAM is \( \overline{CS}_{RAM} = \overline{\overline{A_{15}} + A_{14} + A_{13} + A_{12}} \). For the RAM to be selected (\( \overline{CS}_{RAM} = 0 \)), the input to the final inverter (the output of the OR gate) must be 1. This means \( \overline{A_{15}} + A_{14} + A_{13} + A_{12} = 1 \).
Step 2: Determine the starting address based on the provided answer.
The correct answer suggests the range \( 4000 \, H - 7FFF \, H \). The starting address is \( 4000 \, H \), which in binary is \( 0100 \, 0000 \, 0000 \, 0000_2 \). At this address:
\( A_{15} = 0 \implies \overline{A_{15}} = 1 \)
\( A_{14} = 1 \)
\( A_{13} = 0 \)
\( A_{12} = 0 \)
The OR gate input is \( 1 + 1 + 0 + 0 = 1 \). Thus, \( \overline{CS}_{RAM} = \overline{1} = 0 \), so the RAM is selected at the starting address.
Step 3: Determine the ending address based on the size.
The RAM size is 16 KB = \( 2^{14} \) bytes. Starting from \( 4000 \, H \), the ending address is \( 4000 \, H + (2^{14} - 1) = 4000 \, H + 3FFF \, H = 7FFF \, H \).
Step 4: Verify the chip select for the entire range.
For the range \( 4000 \, H \) (\( 0100..._2 \)) to \( 7FFF \, H \) (\( 0111..._2 \)), \( A_{15} = 0 \) (\( \overline{A_{15}} = 1 \)) and \( A_{14} = 1 \). The OR gate input \( \overline{A_{15}} + A_{14} + A_{13} + A_{12} = 1 + 1 + A_{13} + A_{12} = 1 \). Therefore, \( \overline{CS}_{RAM} = \overline{1} = 0 \) throughout this range.
This interpretation aligns with the provided answer, although it implies that the RAM is selected whenever \( A_{15}=0 \) or \( A_{14}=1 \) (or both), regardless of \( A_{13} \) and \( A_{12} \), which is unusual for standard address decoding where a contiguous block is typically selected. Assuming the question intends this non-standard selection logic to match the provided answer:
