A 4 KB byte-addressable memory is built using four 1 KB memory blocks. IA4 and IA3 feed a decoder that drives the active-high CS of the four blocks; the remaining ten address lines (all except IA4, IA3) go to the Addr inputs of each block. For each block, let \(X_1,X_2,X_3,X_4\) be the input memory address (IA11–IA0), in decimal, of its starting location (Addr \(=0\)). Which option is correct? 
In the design of a control unit of a processor, two common approaches are used: hardware control and microprogrammed control. Consider the following statements:
I. Hardware control units are generally faster but more difficult to modify than microprogrammed control units.
II. In a horizontal microprogrammed control unit, each control signal has a separate bit in the control word.
III. Vertical microprogramming leads to longer control words but provides greater parallelism.
IV. Microprogrammed control units are typically easier to implement and modify than hardware control units.
Consider the following hierarchical cache system with the following access times:
\[ \begin{array}{|c|c|c|} \hline \textbf{Cache Level} & \textbf{Hit Rate} & \textbf{Access Time} \\ \hline L1 & 90\% & 1 \text{ ns} \\ L2 & 80\% & 10 \text{ ns} \\ L3 & 100\% & 100 \text{ ns} \\ \hline \end{array} \]Find \( T_{avg} \) for hierarchical or simultaneous access.
In the diagram, the lines QR and ST are parallel to each other. The shortest distance between these two lines is half the shortest distance between the point P and the line QR. What is the ratio of the area of the triangle PST to the area of the trapezium SQRT?
Note: The figure shown is representative
