Question

A 4-bit synchronous counter with series carry uses flip-flops and two AND gates with propagation delays of 30 ns and 10 ns respectively. The max time between successive clock pulses is:

• A. 10 ns
• B. 30 ns
• C. 40 ns
• D. 50 ns

Hint:

Add delays of all series logic elements and flip-flop to find max clock interval.

Answer 1

The Correct Option is D

Max delay = Delay of flip-flop + total delay of logic gates \[ = 30\ \text{ns (FF)} + 2 \times 10\ \text{ns (AND gates)} = 50\ \text{ns} \]