Question

In FET, as \( V_{GS} \) is changed from zero to increasing reverse bias, the value of \( g_m \) is

• A. \( \text{Increased} \)
• B. \( \text{Decreased} \)
• C. \( \text{Constant} \)
• D. \( \text{Zero} \)

Hint:

In JFETs and depletion-mode MOSFETs, increasing reverse bias on the gate (more negative \( V_{GS} \)) reduces the channel width, which lowers the drain current and thus reduces the transconductance \( g_m \). Always check if the device is enhancement-mode or depletion-mode before assuming the behavior of \( g_m \).

Answer 1

The Correct Option is B

To solve this problem, we need to understand how the transconductance \( g_m \) of a Field-Effect Transistor (FET) changes as the gate-source voltage \( V_{GS} \) is varied.

1. Understanding Transconductance in FET:

- Transconductance (\( g_m \)): In a Field-Effect Transistor (FET), the transconductance \( g_m \) is defined as the rate of change of the drain current \( I_D \) with respect to the gate-source voltage \( V_{GS} \), i.e.,

\[ g_m = \frac{\partial I_D}{\partial V_{GS}} \]

- The value of \( g_m \) depends on the operating region of the FET, particularly in relation to \( V_{GS} \). In an enhancement-mode FET, as \( V_{GS} \) increases, the channel becomes more conductive, and \( g_m \) typically increases as well.

2. Behavior of \( g_m \) as \( V_{GS} \) Changes:

- For \( V_{GS} = 0 \), the FET is typically in the off state, and the drain current \( I_D \) is zero, so the transconductance \( g_m \) is zero.

- As \( V_{GS} \) increases, the channel begins to conduct, and \( g_m \) increases because the drain current becomes more sensitive to changes in \( V_{GS} \).

- As the reverse bias \( V_{GS} \) continues to increase, \( g_m \) may initially increase but eventually saturates or decreases, depending on the type of FET and the voltage threshold.

3. Final Answer:

As \( V_{GS} \) increases from zero to a reverse bias in FETs, the transconductance \( g_m \) typically decreases because the FET moves into the cutoff or sub-threshold region where the drain current becomes less sensitive to the gate voltage.