Question

For n inputs, k product terms and m outputs, the internal logic of the PLA consists of

• A. n+1 buffer gates, k-1 AND gates, m+1 OR gates and m XOR gates
• B. n-1 inverter gates, 2k AND gates, 2m OR gates and m XOR gates
• C. n-1 buffer-inverter gates, 2k AND gates, 2m OR gates and m XOR gates
• D. n buffer-inverter gates, k AND gates, m OR gates and m XOR gates

Hint:

PLA structure: Input buffers/inverters \(\rightarrow\) Programmable AND array (generates product terms) \(\rightarrow\) Programmable OR array (generates sum-of-products outputs).
Some PLAs include programmable XOR gates at the output for polarity control (output can be true or complemented sum-of-products).
Number of inputs = n. Number of product terms = k. Number of outputs = m.

Answer 1

The Correct Option is D

A Programmable Logic Array (PLA) typically consists of two main programmable arrays:

1. AND Array (Product term array): 

This array generates 'k' product terms from the 'n' inputs and their complements. To get both the true and complemented form of each of the 'n' inputs, 'n' buffer/inverter pairs are often used at the input stage. The AND array itself has programmable connections to form 'k' AND gates (product terms).

2. OR Array (Sum term array):

This array takes the 'k' product terms and programmably combines them to form 'm' sum-of-products outputs. This requires 'm' OR gates.

Sometimes, XOR gates are included at the output of the OR gates to provide programmable output polarity (true or complemented output).

Let’s analyze the options based on this general structure:

• Input Stage: For 'n' inputs, to provide both true and complement, 'n' buffer/inverter pairs are typically used. So, 'n' buffer-inverter gates.
• AND Array: To generate 'k' product terms, there are 'k' AND gates.
• OR Array: To generate 'm' output functions (sums of products), there are 'm' OR gates.
• Output Stage (optional): Some PLAs have programmable XOR gates at the output for polarity control (m XOR gates).

Option (d) states: "n buffer-inverter gates, k AND gates, m OR gates and m XOR gates". This aligns with the general structure described, including the optional programmable output XORs.

Let’s check the other options:

• (a) "n+1 buffer gates, k-1 AND gates, m+1 OR gates": Incorrect numbers.
• (b) "n-1 inverter gates, 2k AND gates, 2m OR gates": Incorrect. We need true/complement for all 'n' inputs. Number of AND/OR gates is k and m respectively.
• (c) "n-1 buffer-inverter gates, 2k AND gates, 2m OR gates": Similar issues as (b).

Therefore, option (d) is the most consistent description, assuming the PLA includes programmable output polarity via XOR gates. If it were a simpler PLA without output XORs, the last part would be omitted, but from the choices, (d) is the best fit.

Final Answer:

n buffer-inverter gates, k AND gates, m OR gates and m XOR gates