Consider a sequential digital circuit consisting of T flip-flops and D flip-flops as shown. At the beginning, \(Q_1=0\), \(Q_2=1\), \(Q_3=1\). Which one of the given values of \((Q_1,Q_2,Q_3)\) can NEVER be obtained with this circuit?
Which of the following is a functionally complete set of gates ?
(i) NAND
(ii) NOT
Consider the following hierarchical cache system with the following access times:
\[ \begin{array}{|c|c|c|} \hline \textbf{Cache Level} & \textbf{Hit Rate} & \textbf{Access Time} \\ \hline L1 & 90\% & 1 \text{ ns} \\ L2 & 80\% & 10 \text{ ns} \\ L3 & 100\% & 100 \text{ ns} \\ \hline \end{array} \]Find \( T_{avg} \) for hierarchical or simultaneous access.
In the diagram, the lines QR and ST are parallel to each other. The shortest distance between these two lines is half the shortest distance between the point P and the line QR. What is the ratio of the area of the triangle PST to the area of the trapezium SQRT?
Note: The figure shown is representative
