A 32 bit wide main memory with a capacity of 1 GB is built using 256 m × 4 bits DRAM chips. The number of rows memory cells in the DRAM chip is 214. The time taleen to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milli seconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is_______.